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fm28v102a 1-mbit (64 k 16) f-ram memory cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-91080 rev. *a revised may 7, 2014 2-mbit (128 k 16) f-ram memory features 1-mbit ferroelectric random a ccess memory (f-ram) logically organized as 64 k 16 ? configurable as 128 k 8 using ub and lb ? high-endurance 100 trillion (10 14 ) read/writes ? 151-year data retention (see the data retention and endurance table) ? nodelay? writes ? page mode operatio n to 30-ns cycle time ? advanced high-reliability ferroelectric process sram compatible ? industry-standard 64 k 16 sram pinout ? 60-ns access time, 90-ns cycle time advanced features ? software-programmable block write-protect superior to battery-backed sram modules ? no battery concerns ? monolithic reliability ? true surface mount solution, no rework steps ? superior for moisture, shock, and vibration low power consumption ? active current 7 ma (typ) ? standby current 120 ? a (typ) ? sleep mode current 3 ? a (typ) low-voltage operation: v dd = 2.0 v to 3.6 v industrial temperature: ?40 ? c to +85 ? c 44-pin thin small outline package (tsop) type ii restriction of hazardous substances (rohs) compliant functional overview the fm28v102a is a 64 k 16 n onvolatile memory that reads and writes similar to a standard sram. a ferroelectric random access memory or f-ram is nonvolatile, which means that data is retained after power is removed. it provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed sram (bbsram). fast write timing and high write endurance make the f-ram superior to other types of memory. the fm28v102a operation is si milar to that of other ram devices and therefore, it can be used as a drop-in replacement for a standard sram in a system. read cycles may be triggered by ce or simply by changing the address and write cycles may be triggered by ce or we . the f-ram memory is nonvolatile due to its unique ferroelectric me mory process. these features make the fm28v102a ideal for nonvolatile memory applications requiring frequent or rapid writes. the device is available in a 400-mil 44-pin tsop-ii surface mount package. device specifications are guaranteed over the industrial temperature range ?40 c to +85 c. address latch ce control logic we row decoder a i/o latch & bus driver oe dq 64 k x 16 f-ram array . . . column decoder . . . 15-2 a 1-0 15-0 a 15-0 zz ub, lb logic block diagram
fm28v102a document number: 001-91080 rev. *a page 2 of 20 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 device operation .............................................................. 4 memory operation....................................................... 4 read operation ........................................................... 4 write operation ........................................................... 4 page mode operation ................................................. 4 pre-charge operation.................................................. 4 sleep mode ................................................................. 4 sram drop-in replacement....................................... 5 endurance ................................................................... 6 maximum ratings............................................................. 7 operating range............................................................... 7 dc electrical characteristics .......................................... 7 data retention and endurance ....................................... 8 capacitance ...................................................................... 8 thermal resistance.......................................................... 8 ac test conditions .......................................................... 8 ac switching characteristics ......................................... 9 sram read cycle ...................................................... 9 sram write cycle..................................................... 10 power cycle and sleep mode timing ........................... 14 functional truth table................................................... 15 byte select truth table.................................................. 15 ordering information...................................................... 16 ordering code definitions ...... ................................... 16 package diagram............................................................ 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 document history page ................................................. 19 sales, solutions, and legal information ...................... 20 worldwide sales and design supp ort............. .......... 20 products .................................................................... 20 psoc? solutions ...................................................... 20 cypress developer community................................. 20 technical support .................. ................................... 20
fm28v102a document number: 001-91080 rev. *a page 3 of 20 pinout figure 1. 44-pin tsop ii pinout pin definitions pin name i/o type description a 15 ?a 0 input address inputs : the 16 address lines select one of 64k words in the f-ram array. the lowest two address lines a 1 ?a 0 may be used for page mode read and write operations. dq 15 ?dq 0 input/output data i/o lines : 16-bit bidirectional data bus for accessing the f-ram array. we input write enable : a write cycle begins when we is asserted. the rising edge causes the fm28v102a to write the data on the dq bus to t he f-ram array. the falling edge of we latches a new column address for page mode write cycles. ce input chip enable : the device is selected and a new memory access begins on the falling edge of ce . the entire address is latched internally at this point. subsequent changes to the a 1 ?a 0 address inputs allow page mode operation. oe input output enable : when oe is low, the fm28v102a drives the data bus when the valid read data is available. deasserting oe high tristates the dq pins. ub input upper byte select : enables dq 15 ?dq 8 pins during reads and writes . these pins are hi-z if ub is high. if the user does not perform byte writes and the device is not configured as a 128 k 8, the ub and lb pins may be tied to ground. lb input lower byte select : enables dq 7 ?dq 0 pins during reads and writes. these pins are hi-z if lb is high. if the user does not perform byte writes and the device is not configured as a 128 k 8, the ub and lb pins may be tied to ground. zz input sleep : when zz is low, the device enters a low-power sleep mode for the lowest supply current condition. zz must be high for a normal read/write operation. the zz pin is internally pulled up. v ss ground ground for the device. must be connected to the ground of the system. v dd power supply power supply input to the device. nc no connect no connect. this pin is not connected to the die. v ss dq 6 dq 5 dq 4 v dd a 9 dq 3 a 10 dq 2 dq 1 dq 0 lb a 12 ce a 3 a 2 a 1 a 0 a 15 a 14 a 13 a 11 nc a 8 ub oe a 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44-pin tsop ii top view (not to scale) we dq 7 a 4 v ss v dd dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 ( 16) zz a 6 a 5 v ss
fm28v102a document number: 001-91080 rev. *a page 4 of 20 device operation the fm28v102a is a word wide f-ram memory logically organized as 65,536 16 and accessed using an industry-standard parallel interface. all data written to the part is immediately nonvolatile with no delay. the device offers page mode operation, which provides high-speed access to addresses within a page (row). access to a different page requires that either ce transitions low or the upper address (a 15 ?a 2 ) changes. see the functional truth table on page 15 for a complete description of read and write modes. memory operation users access 65,536 memory locations, each with 16 data bits through a parallel interface. the f-ram array is organized as 16,384 rows each having 64 bits. each row has four column locations, which allow fast access in page mode operation. when an initial address is latched by the falling edge of ce , subsequent column locations may be accessed without the need to toggle ce . when ce is deasserted high, a pre-charge operation begins. writes occur immediately at the end of the access with no delay. the we pin must be toggled for each write operation. the write data is st ored in the nonvolatile memory array immediately, which is a feature unique to f-ram called nodelay writes. read operation a read operation begins on the falling edge of ce . the falling edge of ce causes the address to be latched and starts a memory read cycle if we is high. data becomes available on the bus after the access time is met. when the address is latched and the access completed, a new access to a random location (different row) may begin while ce is still low. the minimum cycle time for random addresses is t rc . note that unlike srams, the fm28v102a's ce -initiated access time is faster than the address access time. the fm28v102a will drive the data bus when oe and at least one of the byte enables (ub , lb ) is asserted low. the upper data byte is driven when ub is low, and the lower data byte is driven when lb is low. if oe is asserted after the memory access time is met, the data bus will be driven with valid data. if oe is asserted before completing the memory access, the data bus will not be driven until valid data is available. this feature minimizes supply current in the sy stem by eliminating transients caused by invalid data being driven to the bus. when oe is deasserted high, the data bus will remain in a hi-z state. write operation in the fm28v102a, writes occur in the same interval as reads. the fm28v102a supports both ce and we controlled write cycles. in both cases, the address a 15 ?a 2 is latched on the falling edge of ce . in a ce -controlled write, the we signal is asserted before beginning the memory cycle. that is, we is low when ce falls. in this case, the device begins the memory cycle as a write. the fm28v102a will not drive the data bus regardless of the state of oe as long as we is low. input data must be valid when ce is deasserted high. in a we -controlled write, the memory cycle begins on the falling edge of ce . the we signal falls some time later. therefore, th e memory cycle begins as a read. the data bus will be driven if oe is low; however, it will be hi-z when we is asserted low. the ce - and we -controlled write timing cases are shown in the switching waveforms on page 13. write access to the array begins on the falling edge of we after the memory cycle is initiated. th e write access terminates on the rising edge of we or ce , whichever comes first. a valid write operation requires the user to m eet the access time specification before deasserting we or ce . the data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of we or ce ). unlike other nonvolatile memory te chnologies, there is no write delay with f-ram. because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. the entire memory operation occurs in a single bus cycle. data polling, a technique used with eeproms to determine if a write is complete, is unnecessary. page mode operation the f-ram array is organized as 16,384 rows each having 64 bits. each row has four column-address locations. address inputs a 1 ?a 0 define the column address to be accessed. an access can start on any column address, and other column locations may be accessed without the need to toggle the ce pin. for fast access reads, after the first data byte is driven to the bus, the column address inputs a 1 ?a 0 may be changed to a new value. a new data byte is then dr iven to the dq pins no later than t aap , which is less than half the initial read access time. for fast access writes, the first write pulse defines the first write access. while ce is low, a subsequent write pulse along with a new column address provides a page mode write access. pre-charge operation the pre-charge operation is an in ternal condition in which the memory state is prepared for a new access. pre-charge is user-initiated by driving the ce signal high. it must remain high for at least the minimum pre-charge time, t pc . pre-charge is also activated by changing the upper addresses, a 15 ?a 2 . the current row is first closed before accessing the new row. the device automatically detects an upper order address change, which starts a pre-charge operation. the new address is latched and the new read data is valid within the t aa address access time; see figure 6 on page 11 . a similar sequence occurs for write cycles; see figure 11 on page 12 . the rate at which random addresses can be issued is t rc and t wc , respectively. sleep mode the device incorporates a sleep mode of operation, which allows the user to achieve the lowest power supply current condition. it enters a low-power sleep mode by asserting the zz pin low. read and write operations must complete before the zz pin going low. when zz is low, all pins are ignored except the zz pin. when zz is deasserted high, there is some time delay (t zzex ) before the user can access the device.
fm28v102a document number: 001-91080 rev. *a page 5 of 20 if sleep mode is not used, the zz pin may be floated (internal pull-up) or tied to v dd . sram drop-in replacement the fm28v102a is designed to be a drop-in replacement for standard asynchronous srams. the device does not require ce to toggle for each new address. ce may remain low indefinitely. while ce is low, the device automatically detects address changes and a new access begins. this functionality allows ce to be grounded, similar to an sram. it also allows page mode operation at speeds up to 33 mhz. figure 3 shows a pull-up resistor on ce , which will keep the pin high during power cycles, assuming the mcu / mpu pin tristates during the reset condition. the pull-up resistor value should be chosen to ensure the ce pin tracks v dd to a high enough value, so that the current drawn when ce is low is not an issue. a 10-k ? resistor draws 330 a when ce is low and v dd = 3.3 v note that if ce is tied to ground, the user must be sure we is not low at power-up or power-down events. if ce and we are both low during power cycles, da ta will be corrupted. figure 4 shows a pull-up resistor on we , which will keep the pin high during power cycles, assuming the mcu/ mpu pin tristates during the reset condition.the pull-up resistor value should be chosen to ensure the we pin tracks v dd to a high enough value, so that the current drawn when we is low is not an issue. a 10-k ? resistor draws 330 a when we is low and v dd = 3.3 v. for applications that require the lowest power consumption, the ce signal should be active (low) only during memory accesses. the fm28v102a draws supply current while ce is low, even if addresses and control signals are static. while ce is high, the device draws no more than the maximum standby current, i sb . the ub and lb byte select pins are active for both read and write cycles. they may be used to a llow the device to be wired as a 128 k 8 memory. the upper and lower data bytes can be tied together and controlled with the byte selects. individual byte enables or the next higher address line a 16 may be available from the system processor. figure 2. sleep/standby state diagram figure 3. use of pull-up resistor on ce initialize normal operation standby sleep power applied zz low zz high ce high, zz high ce low, zz high ce low, zz high zz low ce high, zz high mcu / mpu ce we oe a 15-0 dq 15-0 fm28v102a v dd figure 4. use of pull-up resistor on we figure 5. fm28v102a wired as 128 k x 8 mcu / mpu ce we oe a 15-0 dq 15-0 fm28v102a v dd dq ce ub lb we oe zz 1-mbit f-ram fm28v102a a 15-8 dq 7-0 d 7-0 15-0 a 16 a 15-0
fm28v102a document number: 001-91080 rev. *a page 6 of 20 endurance the fm28v102a is capable of being accessed at least 10 14 times ? reads or writes. an f-ram memory operates with a read and restore mechanism. theref ore, an endurance cycle is applied on a row basis. the f-ram architecture is based on an array of rows and columns. rows are defined by a 15-2 and column addresses by a 1-0 . the array is organized as 16k rows of four words each. the entire row is internally accessed once whether a single 16-bit word or all four words are read or written. each word in the row is counted only once in an endurance calculation. the user may choose to write cpu instructions and run them from a certain address space. table 1 shows endurance calculations for a 256-byte repeating loop, which includes a starting address, three-page mode accesses, and a ce pre-charge. the number of bus clock cycles needed to complete a four-word transaction is 4 + 1 at lower bus speeds, but 5 + 2 at 33 mhz due to initial read latency and an extra clock cycle to satisfy the device's pre-charge timing constraint t pc . the entire loop causes each byte to experience only one endurance cycle. the f-ram read and write enduranc e is virtually unlimited even at a 33-mhz system bus clock rate. table 1. time to reach 100 trillion cycles for repeating 256-byte loop bus freq (mhz) bus cycle time (ns) 256-byte transaction time ( ? s) endurance cycles/sec endurance cycles/year years to reach 10 14 cycles 33 30 10.56 94,690 2.98 x 10 12 33.5 25 40 12.8 78,125 2.46 x 10 12 40.6 10 100 28.8 34,720 1.09 x 10 12 91.7 5 200 57.6 17,360 5.47 x 10 11 182.8
fm28v102a document number: 001-91080 rev. *a page 7 of 20 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 ? c to +125 ? c maximum junction temperature ................................... 95 ? c supply voltage on v dd relative to v ss ........?1.0 v to + 4.5 v voltage applied to outputs in high z state .................................... ?0.5 v to v dd + 0.5 v input voltage .......... ?1.0 v to + 4.5 v and v in < v dd + 1.0 v transient voltage (< 20 ns) on any pin to ground potential ............ ..... ?2.0 v to v cc + 2.0 v package power dissipation capability (t a = 25 c) ................................................. 1.0 w surface mount pb soldering temperature (3 seconds) ........ .............. .............. ..... +260 ? c dc output current (1 output at a time, 1s duration) .... 15 ma static discharge voltage human body model (aec-q100-002 rev. e) ............... 2 kv charged device model (aec-q100-011 rev. b) ......... 500 v latch-up current ................................................... > 140 ma operating range range ambient temperature (t a ) v dd industrial ?40 ? c to +85 ? c 2.0 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [1] max unit v dd power supply voltage 2.0 3.3 3.6 v i dd v dd supply current v dd = 3.6 v, ce cycling at min. cycle time. all inputs toggling at cmos levels (0.2 v or v dd ? 0.2 v), all dq pins unloaded. ?712ma i sb standby current v dd = 3.6 v, ce at v dd , all other pins are static and at cmos levels (0.2 v or v dd ? 0.2 v), zz is high t a = 25 ? c ? 120 150 a t a = 85 ? c? ? 250a i zz sleep mode current v dd = 3.6 v, zz is low, all other inputs v ss or v dd . t a = 25 ? c?35a t a = 85 ? c??8a i li input leakage current v in between v dd and v ss ??+ 1a i lo output leakage current v out between v dd and v ss ??+ 1a v ih1 input high voltage v dd = 2.7 v to 3.6 v 2.2 ? v dd + 0.3 v v ih2 input high voltage v dd = 2.0 v to 2.7 v 0.7 v dd ??v v il1 input low voltage v dd = 2.7 v to 3.6 v ? 0.3 ? 0.8 v v il2 input low voltage v dd = 2.0 v to 2.7 v ? 0.3 ? 0.3 v dd v v oh1 output high voltage i oh = ?1 ma, v dd > 2.7 v 2.4 ? ? v v oh2 output high voltage i oh = ?100 a v dd ? 0.2 ? ? v v ol1 output low voltage i ol = 2 ma, v dd > 2.7 v ? ? 0.4 v v ol2 output low voltage i ol = 150 a ? ? 0.2 v r in [2] input resistance (zz pin) for v in = v ih (min) 40 ? ? k ? for v in = v il (max) 1??m ? notes 1. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 2. the input pull-up circuit is strong (> 40 k ? ) when the input voltage is above v ih and weak (> 1 m ? ) when the input voltage is below v il .
fm28v102a document number: 001-91080 rev. *a page 8 of 20 ac test conditions input pulse levels ...................................................0 v to 3 v input rise and fall times (10%?90%) ........................... < 3 ns input and output timing reference levels ....................... 1.5 v output load capacitance ............................................... 30 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 85 ? c 10 ? years t a = 75 ? c38? t a = 65 ? c151? nv c endurance over operating temperature 10 14 ? cycles capacitance parameter description test conditions max unit c i/o input/output capacitance (dq) t a = 25 ? c, f = 1 mhz, v dd = v dd(typ) 8pf c in input capacitance 6pf c zz input capacitance of zz pin 8 pf thermal resistance parameter description test conditions 44-pin tsop ii unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with eia/jesd51. 107 ? c/w ? jc thermal resistance (junction to case) 25 ? c/w
fm28v102a document number: 001-91080 rev. *a page 9 of 20 ac switching characteristics over the operating range parameters [3] description v dd = 2.0 v to 2.7 v v dd = 2.7 v to 3.6 v unit cypress parameter alt parameter min max min max sram read cycle t ce t ace chip enable access time ? 70 ? 60 ns t rc ? read cycle time 105 ? 90 ns t aa ? address access time, a 15-2 ?105? 90 ns t oh t oha output hold time, a 15-2 20 ? 20 ? ns t aap ? page mode access time, a 1-0 ?40 ? 30 ns t ohp ? page mode output hold time, a 1-0 3? 3 ? ns t ca ? chip enable active time 70 ? 60 ? ns t pc ? pre-charge time 35 ? 30 ? ns t ba t bw ub , lb access time ? 25 ? 15 ns t as t sa address setup time (to ce low) 0? 0 ? ns t ah t ha address hold time (ce controlled) 70 ? 60 ? ns t oe t doe output enable access time ? 25 ? 15 ns t hz [4, 5] t hzce chip enable to output hi-z ? 15 ? 10 ns t ohz [4, 5] t hzoe output enable high to output hi-z ? 15 ? 10 ns t bhz [4, 5] t hzbe ub , lb highhigh to output hi-z ? 15 ? 10 ns notes 3. test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 0 to 3 v, output loading of the specified i ol /i oh and load capacitance shown in ac test conditions on page 8 . 4. t hz , t ohz and t bhz are specified with a load capacitance of 5 pf. transition is measured when the outputs enter a high impedance state. 5. this parameter is characterized but not 100% tested.
fm28v102a document number: 001-91080 rev. *a page 10 of 20 sram write cycle t wc t wc write cycle time 105 ? 90 ? ns t ca ? chip enable active time 70 ? 60 ? ns t cw t sce chip enable to write enable high 70 ? 60 ? ns t pc ? pre-charge time 35 ? 30 ? ns t pwc ? page mode write enable cycle time 40 ? 30 ? ns t wp t pwe write enable pulse width 22 ? 18 ? ns t wp2 t bw ub , lb pulse width 22 ? 18 ? ns t wp3 t pwe we low to ub , lb high 22 ? 18 ? ns t as t sa address setup time (to ce low) 0 ? 0 ? ns t ah t ha address hold time (ce controlled) 70 ? 60 ? ns t asp ? page mode address setup time (to we low) 8 ? 5 ? ns t ahp ? page mode address hold time (to we low) 20 ? 15 ? ns t wlc t pwe write enable low to chip disabled 30 ? 25 ? ns t blc t bw ub , lb low to chip disabled 30 ? 25 ? ns t wla ? write enable low to address change, a 15-2 30 ? 25 ? ns t awh ? address change to write enable high, a 15-2 105 ? 90 ? ns t ds t sd data input setup time 20 ? 15 ? ns t dh t hd data input hold time 0 ? 0 ? ns t wz [6, 7] t hzwe write enable low to output hi-z ? 10 ? 10 ns t wx [7] ? write enable high to output driven 8 ? 5 ? ns t bds ? byte disable setup time (to we low) 8 ? 5 ? ns t bdh ? byte disable hold time (to we high) 8 ? 5 ? ns ac switching characteristics (continued) over the operating range parameters [3] description v dd = 2.0 v to 2.7 v v dd = 2.7 v to 3.6 v unit cypress parameter alt parameter min max min max notes 6. t wz is specified with a load c apacitance of 5 pf. trans ition is measured when the ou tputs enter a high impedance state. 7. this parameter is characterized but not 100% tested.
fm28v102a document number: 001-91080 rev. *a page 11 of 20 figure 6. read cycle timing 1 (ce low, oe low) figure 7. read cycle timing 2 (ce controlled) figure 8. page mode read cycle timing [8] t aa previous data valid data t oh valid data t aa t oh dq 15-0 a t rc t rc 15-2 t as a dq t ce t hz t oe t oh t ohz ub / lb oe ce t ba t bhz t ca t pc t ah 15-0 15-0 t as t hz t aap t ohp ce a oe dq t ca a t oe t ce t ohz t pc data 0 data 1 data 2 col 0 col 1 col 2 15-2 1-0 15-0 note 8. although sequential column addressing is shown, it is not required
fm28v102a document number: 001-91080 rev. *a page 12 of 20 figure 9. write cycle timing 1 (we controlled) [9] figure 10. write cycle timing 2 (ce controlled) figure 11. write cycle timing 3 (ce low) [9] t wz t hz d in ce a we t ca t pc dq t wp t cw t as d out d out t ds t dh t wlc 15-0 15-0 t wx ce a we dq t as t dh t ds d in t ca t pc ub/lb t blc 15-0 15-0 t dh t wx d out d in a we dq t wc t wla t ds t awh d out t wz d in 15-0 15-0 note 9. oe (not shown) is low only to show the effect of we on dq pins.
fm28v102a document number: 001-91080 rev. *a page 13 of 20 figure 12. write cycle timing 4 (ce low) [10] figure 13. page mode write cycle timing t bds t dh d in a we dq t wp3 d in ub/lb t wp2 t ds t dh t ds t bdh 15-0 15-0 t asp t dh ce a we t ca t pc t cw col 0 col 1 data 0 col 2 t as t ds data 1 t wp data 2 oe t ahp t pwc t wlc 15-2 a 1-0 dq 15-0 note 10. ub and lb to show byte enable and byte masking cases.
fm28v102a document number: 001-91080 rev. *a page 14 of 20 power cycle and sleep mode timing over the operating range parameter description min max unit t pu power-up (after v dd min. is reached) to first access time 1 ? ms t pd last write (we high) to power down time 0 ? s t vr [11] v dd power-up ramp rate 50 ? s/v t vf [11] v dd power-down ramp rate 100 ? s/v t zzh zz active to dq hi-z time ? 20 ns t wezz last write to sleep mode entry time 0 ? s t zzl zz active low time 1 ? s t zzen sleep mode entry time (zz low to ce don?t care) ? 0 s t zzex sleep mode exit time (zz high to 1 st access after wakeup) ? 450 s figure 14. power cycle and sleep mode timing zz v dd min. v dd we t pd ce dq r/w allowed t wezz t pu d out t zzh d in t zzex r/w allowed t zzen r/w allowed t zzex v dd min. t zzl t vr t vf note 11. slope measured at any point on the v dd waveform.
fm28v102a document number: 001-91080 rev. *a page 15 of 20 functional truth table ce we a 15-2 a 1-0 zz operation [12, 13] x x x x l sleep mode h x x x h standby/idle l h h v v v v h h read l h no change change h page mode read l h change v h random read l l l v v v v h h ce -controlled write [13] l vvhwe -controlled write [13, 14] l no change v h page mode write [15] l x x x x x x h h starts pre-charge byte select truth table we oe lb ub operation [16] h h x x read; outputs disabled xhh h l h l read upper byte; hi-z lower byte l h read lower byte; hi-z upper byte l l read both bytes l x h l write upper byte; mask lower byte l h write lower byte; mask upper byte l l write both bytes notes 12. h = logic high, l = logic low, v = valid data, x = don't care, = toggle low, = toggle high. 13. for write cycles, data-in is latched on the rising edge of ce or we , whichever comes first. 14. we -controlled write cycle begins as a read cycle and then a 15-2 is latched. 15. addresses a 1-0 must remain stable for at least 15 ns during page mode operation. 16. the ub and lb pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 128 k x 8.
fm28v102a document number: 001-91080 rev. *a page 16 of 20 ordering code definitions ordering information access time (ns) ordering code package diagram package type operating range 60 FM28V102A-TG 51-85087 44-pin tsop ii industrial FM28V102A-TGtr all the above parts are pb-free. option: blank = standard; tr = tape and reel package type: tg = 44-pin tsop ii die revision: a density: 102 = 1-mbit voltage: v = 2.0 v to 3.6 v parallel f-ram cypress 28 fm v 102 a - tg tr
fm28v102a document number: 001-91080 rev. *a page 17 of 20 package diagram figure 15. 44-pin tsop package outline, 51-85087 51-85087 *e
fm28v102a document number: 001-91080 rev. *a page 18 of 20 acronyms document conventions units of measure acronym description ub upper byte lb lower byte ce chip enable cmos complementary metal oxide semiconductor eia electronic industries alliance f-ram ferroelectric random access memory i/o input/output oe output enable rohs restriction of hazardous substances rw read and write sram static random access memory tsop thin small outline package we write enable symbol unit of measure c degree celsius hz hertz khz kilohertz k ? kilohm mhz megahertz ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond m ? megaohm ns nanosecond ? ohm % percent pf picofarad v volt w watt
fm28v102a document number: 001-91080 rev. *a page 19 of 20 document history page document title: fm28v102a, 1-mbit (64 k 16) f-ram memory document number: 001-91080 rev. ecn no. orig. of change submission date description of change ** 4272603 gvch 03/11/2014 new data sheet. *a 4372700 gvch 05/07/2014 changed datasheet status from ?preliminary to final? maximum ratings : static discharge voltage removed machine model dc electrical characteristics : updated i zz test condition updated figure 6 for more clarity removed FM28V102A-TGes part
document number: 001-91080 rev. *a revised may 7, 2014 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. fm28v102a ? cypress semiconductor corporation, 2014. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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